Add basic CPU-related ideas.

4 files changed, 79 insertions, 0 deletions

diff --git a/cpu/registers/config.txt b/cpu/registers/config.txt
new file mode 100644
index 0000000..2be32a1
--- /dev/null
+++ b/cpu/registers/config.txt
@@ -0,0 +1,50 @@
+MR (Mode Register)
+	CPU mode (16-bit, 32-bit, 64-bit, etc)
+
+	Adjusts size according to current CPU mode
+
+	On read
+		Gives supported modes
+			If ((1 << ([desired mode in bytes] - 1)) & cr0) != 0, then it is supported
+
+			Support for 16-bit mode, 64-bit mode, 128-bit mode, and 256 bit mode would be represented as 111010b
+
+	On write
+		Sets current mode
+			Follows the same pattern as reading
+			100b would represent 32-bit mode
+
+		Only one bit is allowed to be set
+			Triggers <TODO> exception otherwise
+
+		No need for a jump instruction immediately after it
+
+PR (Privilege Register)
+	Consists of flags for specific privileges
+		Bit 0: Can configure everything
+		All other bits are to be configured at runtime
+
+	CPU initializes with it set to all 1s
+	Always readable
+	Writing directly is only allowed to remove permissions
+		Triggers <TODO> exception otherwise
+
+	Additional privileges can be granted by interrupts, exceptions and IRQs as configured by the IDT, EDT and IRQT, respectively
+
+FR (Feature Register)
+	Consists of various bit flags for different features that are currently enabled
+
+	See features/all.txt for a full list
+
+	Read only
+
+OFR (Optional Feature Register)
+	Consists of various bit flags for different features that can be enabled/disabled at runtime
+
+	See features/all.txt for a full list
+
+	On read:
+		Lists features that can be enabled/disabled
+
+	On write:
+		Sets the configurable features, and ignores bits for non-configurable ones
diff --git a/cpu/registers/general.txt b/cpu/registers/general.txt
new file mode 100644
index 0000000..1580fbf
--- /dev/null
+++ b/cpu/registers/general.txt
@@ -0,0 +1,13 @@
+There are <n> integer registers, named R0-<n-1>
+	All use two's compliment
+
+	There is an additional register, RS (Register Selector), that offsets the register number from its base
+		This register only has <bits required to store n-1> bits, and its overflow is never recorded
+
+	There is an additional register, RW (Register Window), that controls the number of integer registers available and preserved
+
+There are <n> float registers, named F0-<n-1>
+	There is an additional register, FS (Float Selector), that offsets the register number from its base
+		This register only has <bits required to store n-1> bits, and its overflow is never recorded
+
+	There is an additional register, FW (Float Window), that controls the number of float registers available and preserved
diff --git a/cpu/registers/hardware-interrupt-related.txt b/cpu/registers/hardware-interrupt-related.txt
new file mode 100644
index 0000000..895ff92
--- /dev/null
+++ b/cpu/registers/hardware-interrupt-related.txt
@@ -0,0 +1,5 @@
+OIP (Old Instruction Pointer)
+	Used to store the old IP when interrupts occur
+
+OPR (Old Privilege Register)
+	Used to store the old PR when interrupts occur
diff --git a/cpu/registers/pointers.txt b/cpu/registers/pointers.txt
new file mode 100644
index 0000000..e02db04
--- /dev/null
+++ b/cpu/registers/pointers.txt
@@ -0,0 +1,11 @@
+IP (Instruction Pointer)
+	Pointer to the current instruction being executed
+	It is not directly affected by OR
+
+	Read-only, can be set by certain jump instructions
+
+SP (Stack Pointer)
+	Pointer to the bottom of the stack (grows down) (used implicitly by push/pop instructions)
+
+BP (Base Pointer)
+	Pointer to the top of the stack (grows down) (used implicitly by push/pop instructions)