From 8b4b6b2a3048aa5bfa369e58ec020706b543cb72 Mon Sep 17 00:00:00 2001 From: Test_User Date: Wed, 26 Apr 2023 02:22:28 -0400 Subject: Fill in some exceptions --- cpu/exceptions/list.txt | 7 +++++++ cpu/instructions/opcode.txt | 2 +- cpu/registers/config.txt | 4 ++-- cpu/task_switching/execution.txt | 24 ++++++++++++------------ 4 files changed, 22 insertions(+), 15 deletions(-) create mode 100644 cpu/exceptions/list.txt diff --git a/cpu/exceptions/list.txt b/cpu/exceptions/list.txt new file mode 100644 index 0000000..8b38201 --- /dev/null +++ b/cpu/exceptions/list.txt @@ -0,0 +1,7 @@ +0: Division by zero +1: Illegal instruction (used in cases where it is never valid) +2: Invalid operation (used in cases where it is only invalid in this context) +3: Access violation + +4: Double exception +5: Page fault diff --git a/cpu/instructions/opcode.txt b/cpu/instructions/opcode.txt index 607fa6c..97cc16b 100644 --- a/cpu/instructions/opcode.txt +++ b/cpu/instructions/opcode.txt @@ -24,4 +24,4 @@ is_conditional: Exceptions: If (s+2) > n: - TODO: make exception list + Triggers `illegal instruction` exception diff --git a/cpu/registers/config.txt b/cpu/registers/config.txt index d32a47e..d252765 100644 --- a/cpu/registers/config.txt +++ b/cpu/registers/config.txt @@ -15,7 +15,7 @@ MR (Mode Register) 100b would represent 32-bit mode Only one bit is allowed to be set - Triggers exception otherwise + Triggers `invalid operation` exception otherwise No need for a jump instruction immediately after it @@ -27,7 +27,7 @@ PR (Privilege Register) CPU initializes with it set to all 1s Always readable Writing directly is only allowed to remove permissions - Triggers exception otherwise + Triggers `access violation` exception otherwise Additional privileges can be granted by interrupts, exceptions and IRQs as configured by the IDT, EDT and IRQT, respectively diff --git a/cpu/task_switching/execution.txt b/cpu/task_switching/execution.txt index 63a9126..78f587c 100644 --- a/cpu/task_switching/execution.txt +++ b/cpu/task_switching/execution.txt @@ -1,15 +1,15 @@ All task switches will occur after the current instructions in the queue have finished being processed and written Will not conflict with other writes within the same instruction queue - Triggers exception if multiple task switches occur within the same instruction queue + Triggers `illegal instruction` exception if multiple task switches occur within the same instruction queue TODO: mark current CPU executing it Call process: Only allowed to be used by the original process - Triggers exception otherwise + Triggers `invalid operation` exception otherwise Custom ID must match between the tdt at the index and the one specified by the instruction, and the target must be marked as valid - TODO: trigger exception? set a flag? + Sets the `zero` flag and skips execution of this instruction otherwise One segment may be passed to the callee, used by the callee with all segment bits set Caller may call with all segment bits set to not pass a segment @@ -24,7 +24,7 @@ Call process: Return process: Only allowed to be used by the callee - Triggers exception otherwise + Triggers `invalid operation` exception otherwise Segments will be loaded from the tdt Process id in the tdt is set to the original process's id @@ -35,27 +35,27 @@ Return process: Switch process: Only allowed to be used by the original process - Triggers exception otherwise + Triggers `invalid operation` exception otherwise Only allowed to switch to a process that is not currently active - TODO: trigger exception? set a flag? + Sets the `zero` flag and skips execution of this instruction otherwise Custom ID must match between the tdt at the index and the one specified by the instruction, and the target must be marked as valid - TODO: trigger exception? set a flag? + Sets the `zero` flag and skips execution of this instruction otherwise All registers are saved to the current tdt and loaded from the target's tdt index Loads all registers from the target's tdt index Switch process and exit exception/interrupt handler: - Only allowed to be used while in an exception/interrupt handler (TODO: different opcode for each?) - Triggers exception otherwise + Only allowed to be used while in an exception/interrupt handler + Triggers `invalid operation` exception otherwise Only allowed to switch to a process that is not currently active - TODO: trigger exception? set a flag? + Sets the `zero` flag and skips execution of this instruction otherwise - Only allowed to switch to a process that is valid - TODO: trigger exception? set a flag? + Custom ID must match between the tdt at the index and the one specified by the instruction, and the target must be marked as valid + Sets the `zero` flag and skips execution of this instruction otherwise All registers are saved to the current tdt and loaded from the target's tdt index IP and PR are saved as if all exception/interrupt handlers returned -- cgit v1.2.3