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| author | Test_User <hax@andrewyu.org> | 2023-05-14 14:19:36 -0400 |
|---|---|---|
| committer | Test_User <hax@andrewyu.org> | 2023-05-14 14:19:36 -0400 |
| commit | 1e6377c101b17cb4b6140ef24d673e47e41cfa22 (patch) | |
| tree | 036e093e3305c95821027627ce603232a24dd988 | |
| parent | fd9a62701e4048ac6004052471d58f6383597fa0 (diff) | |
| download | specification-1e6377c101b17cb4b6140ef24d673e47e41cfa22.tar.gz specification-1e6377c101b17cb4b6140ef24d673e47e41cfa22.zip | |
Fix definition for MR
| -rw-r--r-- | cpu/registers/config.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/registers/config.txt b/cpu/registers/config.txt index 9ae7bbb..4fe8f42 100644 --- a/cpu/registers/config.txt +++ b/cpu/registers/config.txt @@ -5,7 +5,7 @@ MR (Mode Register) On read Gives supported modes - If ((1 << ([desired mode in bytes] - 1)) & MR) != 0, then it is supported + If ((1 << log_2([desired mode in bits / 8])) & MR) != 0, then it is supported Support for 16-bit mode, 64-bit mode, 128-bit mode, and 256 bit mode would be represented as 111010b |