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authorTest_User <hax@andrewyu.org>2023-04-26 15:01:37 -0400
committerTest_User <hax@andrewyu.org>2023-04-26 15:01:37 -0400
commit868e583b8d8c7dbeb8478202ea38b7de3f64e151 (patch)
tree689eb98eb36bba660b603233f6b8551d93fada7d
parent8b4b6b2a3048aa5bfa369e58ec020706b543cb72 (diff)
downloadspecification-868e583b8d8c7dbeb8478202ea38b7de3f64e151.tar.gz
specification-868e583b8d8c7dbeb8478202ea38b7de3f64e151.zip
Add iret* instructions
-rw-r--r--cpu/instructions/execution_control/iretde.txt14
-rw-r--r--cpu/instructions/execution_control/irete.txt14
-rw-r--r--cpu/instructions/execution_control/ireth.txt14
-rw-r--r--cpu/interrupts/execution.txt2
4 files changed, 43 insertions, 1 deletions
diff --git a/cpu/instructions/execution_control/iretde.txt b/cpu/instructions/execution_control/iretde.txt
new file mode 100644
index 0000000..9e13fa5
--- /dev/null
+++ b/cpu/instructions/execution_control/iretde.txt
@@ -0,0 +1,14 @@
+Number of parameters: 0
+
+Usage:
+ iretde
+
+Effect:
+ ../../exceptions/execution.txt
+
+ IP is set to OIPDE
+ PR is set to OPRDE
+ Will be considered to be in the previous exception handler
+
+Exceptions:
+ `Invalid operation` if not currently executing a double excetion handler
diff --git a/cpu/instructions/execution_control/irete.txt b/cpu/instructions/execution_control/irete.txt
new file mode 100644
index 0000000..273ea59
--- /dev/null
+++ b/cpu/instructions/execution_control/irete.txt
@@ -0,0 +1,14 @@
+Number of parameters: 0
+
+Usage:
+ irete
+
+Effect:
+ ../../exceptions/execution.txt
+
+ IP is set to OIPE
+ PR is set to OPRE
+ No longer considered to be in an exception handler
+
+Exceptions:
+ `Invalid operation` if not currently executing an excetion handler
diff --git a/cpu/instructions/execution_control/ireth.txt b/cpu/instructions/execution_control/ireth.txt
new file mode 100644
index 0000000..54c92c8
--- /dev/null
+++ b/cpu/instructions/execution_control/ireth.txt
@@ -0,0 +1,14 @@
+Number of parameters: 0
+
+Usage:
+ ireth
+
+Effect:
+ ../../interrupts/execution.txt
+
+ IP is set to OIPH
+ PR is set to OPRH
+ Hardware interrupts are allowed again
+
+Exceptions:
+ `Invalid operation` if not currently executing a hardware interrupt
diff --git a/cpu/interrupts/execution.txt b/cpu/interrupts/execution.txt
index 858334c..dcff30e 100644
--- a/cpu/interrupts/execution.txt
+++ b/cpu/interrupts/execution.txt
@@ -3,7 +3,7 @@ When an interrupt occurs:
OIPI gets set to the IP from the previous code running
PR is set to all 1s
-The next interrupt will not occur until after the current processing has been finished via `ireti`
+The next interrupt will not occur until after the current processing has been finished via `ireth`
When returning via ireth:
PR is set to OPRI