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* License clarificationAndrew Yu2023-07-131-0/+10
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* Add some parameter types, make parameters a dynamic size without harming cpu ↵Test_User2023-06-172-30/+83
| | | | readablity too much
* LICENSE: It is 2023Andrew Yu2023-06-161-2/+2
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* Add a bunch of fewer-parameter versions of instructions, specify that ↵Test_User2023-06-1421-0/+178
| | | | special returns only take effect after other writes complete
* Bit of change to parameters, and fixing it to actually say what I meant; ↵Test_User2023-06-142-5/+11
| | | | more assembler progress as well
* Change instruction format a bit, continue assembler writingTest_User2023-06-121-5/+5
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* Explicitly define some more stuffTest_User2023-06-112-3/+3
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* Add config-related instructions, specify what happens if an IRQ that isn't ↵Test_User2023-06-115-0/+47
| | | | handled is given
* Fix subtract parameter ordering, add .gitignore for active nanoTest_User2023-06-102-2/+2
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* Fix definition for MRTest_User2023-05-141-1/+1
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* Define instructions' parameter formatTest_User2023-04-291-0/+31
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* Define booting (mostly), fix reference in OFRTest_User2023-04-296-1/+27
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* Clearly define addressing translation, add some default segments, remove ↵Test_User2023-04-282-1/+13
| | | | read-only restriction from IP
* Put task-related instructions into instructions/, get rid of the term ↵Test_User2023-04-267-14/+75
| | | | "process" where "task" was meant
* Add iret* instructionsTest_User2023-04-264-1/+43
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* Fill in some exceptionsTest_User2023-04-264-15/+22
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* Fix one ) placement, fix exception conditionTest_User2023-04-261-2/+2
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* Add less-braindead paging idea as an optional feature (incomplete)Test_User2023-03-193-0/+27
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* Add data transfer instructionsTest_User2023-03-195-0/+44
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* Add bitwise instructionsTest_User2023-02-1610-0/+94
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* Finish adding basic arithmetic instructionsTest_User2023-02-166-0/+68
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* Use parameter size, not current CPU modeTest_User2023-02-151-2/+6
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* Make conditional stuff work nicelyTest_User2023-02-153-78/+32
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* Add more instructionsTest_User2023-02-157-0/+74
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* Rewrite/improve conditional instructionsTest_User2023-02-134-46/+26
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* All general-purpose registers can be used for integer arithmatic or ↵Test_User2023-01-211-11/+6
| | | | floating-point arithmatic, no need to seperate them
* Add hardware task switching, get rid of software interruptsTest_User2023-01-0511-34/+103
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* more segments, fewer addresses (and 64-bit mode is outgrown... use 128-bit mode)Test_User2023-01-031-6/+6
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* Started listing instructions, improved cpu readability of format A a littleTest_User2022-11-226-2/+73
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* More VLIW format ideasTest_User2022-11-171-1/+19
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* Dynamic VLIW definition continued, fixed another missing thingTest_User2022-11-162-0/+10
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* Added incomplete instruction set overview, fixed some other stuffTest_User2022-11-147-6/+48
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* added basics for exceptions (incomplete)Test_User2022-10-085-9/+54
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* Add basic CPU-related ideas.Test_User2022-10-0714-0/+192
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