Add basic CPU-related ideas.

14 files changed, 192 insertions, 0 deletions

diff --git a/cpu/LICENSE b/cpu/LICENSE
new file mode 100644
index 0000000..b4d6b4e
--- /dev/null
+++ b/cpu/LICENSE
@@ -0,0 +1,5 @@
+Copyright (C) 2022
+Andrew Yu <andrew@andrewyu.org>
+Test_User <hax@andrewyu.org>
+
+All rights reserved
diff --git a/cpu/access_control/gdt.txt b/cpu/access_control/gdt.txt
new file mode 100644
index 0000000..fcadb5d
--- /dev/null
+++ b/cpu/access_control/gdt.txt
@@ -0,0 +1,70 @@
+Each entry is n*4 bits long, where n is the current mode in bits
+TODO: Specifiy a limit for them
+
+It uses the following format:
+	(higher address)
+	+---------------------+-------------------------+
+	| upper 4 bits: flags | lower 3/4: base address |
+	+---------------------+-------------------------+
+	| upper 4 bits: type  | lower 3/4: limit        |
+	+---------------------+-------------------------+
+	| permissions required to use                   |
+	+-----------------------------------------------+
+	| permissions not allowed to use                |
+	+-----------------------------------------------+
+	(lower address)
+
+Unspecified bits are ignored for the gdt's purposes
+
+type: 
+	0: null, inactive
+	1: <normal>
+	???
+
+flags for <normal> type segments:
+	3: invert region access (specifies a region of memory not allowed for this entry)
+	2: readable
+	1: writable
+	0: executable
+
+base address:
+	This number is added to the address for all pointers referencing this segment
+
+limit:
+	This is the maximum value allowed for the address of the pointer referencing this segment
+
+permissions required to use:
+	The active task must have all of the permissions set here to use this segment
+
+permissions not allowed to use:
+	The active task must not have any of these permissions to use this segment
+
+32-bit example:
+	 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
+	+------------------------------------------------------------------------------------------------+
+	| 0  1  0  0  0  0  0  0  1  0  0  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 |
+	| 0  0  0  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  1  0  0  0  0  0  0  0  0  0  0 |
+	| 1  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 |
+	| 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  1  1  0 |
+	+------------------------------------------------------------------------------------------------+
+
+flags: 0 1 0 0
+	not inverted
+	readable
+	not writable
+	not executable
+
+base address: 1  0  0  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
+	0x900000
+
+type: 0 0 0 1
+	type 1: <normal>
+
+limit: 0  0  0  0  0  0  0  0  0  0  0  0  0  1  0  0  0  0  0  0  0  0  0  0
+	0x400
+
+permissions required: 1  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
+	must have 31st permission to use this segment
+
+permissions not allowed: 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  1  1  0
+	must not have 1st or 2nd permission to use this segment
diff --git a/cpu/features/all.txt b/cpu/features/all.txt
new file mode 100644
index 0000000..14f5795
--- /dev/null
+++ b/cpu/features/all.txt
@@ -0,0 +1 @@
+Hardware task switching
diff --git a/cpu/interrupts/hardware/execution.txt b/cpu/interrupts/hardware/execution.txt
new file mode 100644
index 0000000..c3cc5f5
--- /dev/null
+++ b/cpu/interrupts/hardware/execution.txt
@@ -0,0 +1,10 @@
+When a hardware interrut occurs:
+	OPR gets set to the PR from the previous code running
+	OIP gets set to the IP from the previous code running
+	PR is set to all 1s
+
+The next hardware interrupt will not occur until after the current processing has been finished via `ireth`
+
+When returning via ireth:
+	PR is set to OPR
+	Execution jumps to OIP
diff --git a/cpu/interrupts/hardware/irqt.txt b/cpu/interrupts/hardware/irqt.txt
new file mode 100644
index 0000000..f1f5792
--- /dev/null
+++ b/cpu/interrupts/hardware/irqt.txt
@@ -0,0 +1,4 @@
+Each entry is n bits long, where n is the current mode in bits
+TODO: Specify a limit for them
+
+Each entry is a pointer to the code to be executed
diff --git a/cpu/interrupts/software/execution.txt b/cpu/interrupts/software/execution.txt
new file mode 100644
index 0000000..0cad31b
--- /dev/null
+++ b/cpu/interrupts/software/execution.txt
@@ -0,0 +1,8 @@
+When calling a software interrupt:
+	R0 gets overwritten with the current PR
+	R1 gets overwritten with a pointer of the same segment as IP, pointing to the next instruction
+	PR is set to all 1s
+
+When returning via iretp:
+	PR is set to R0
+	Execution jumps to R1
diff --git a/cpu/interrupts/software/idt.txt b/cpu/interrupts/software/idt.txt
new file mode 100644
index 0000000..04cafd9
--- /dev/null
+++ b/cpu/interrupts/software/idt.txt
@@ -0,0 +1,11 @@
+Each enty is n*2 bits long, where n is the current mode in bits
+TODO: Specify a limit for them
+
+It uses the following format:
+	(higher address)
+	+--------------------------------+
+	| Pointer to executable code run |
+	+--------------------------------+
+	| Privileges required for usage  |
+	+--------------------------------+
+	(lower address)
diff --git a/cpu/messages/tips.txt b/cpu/messages/tips.txt
new file mode 100644
index 0000000..2913c75
--- /dev/null
+++ b/cpu/messages/tips.txt
@@ -0,0 +1,2 @@
+White_Flame | but you do need to consider if you can lower the overhead of calling supervisor code, and passing messages between processes
+13:06:53          * | \Test_User gets to reading about spectre/meltdown and adds a "GDTs/LDTs are stored directly on the CPU when loaded, and any speculation must check access first, and only to fetch/execute if it is allowed"
diff --git a/cpu/registers/config.txt b/cpu/registers/config.txt
new file mode 100644
index 0000000..2be32a1
--- /dev/null
+++ b/cpu/registers/config.txt
@@ -0,0 +1,50 @@
+MR (Mode Register)
+	CPU mode (16-bit, 32-bit, 64-bit, etc)
+
+	Adjusts size according to current CPU mode
+
+	On read
+		Gives supported modes
+			If ((1 << ([desired mode in bytes] - 1)) & cr0) != 0, then it is supported
+
+			Support for 16-bit mode, 64-bit mode, 128-bit mode, and 256 bit mode would be represented as 111010b
+
+	On write
+		Sets current mode
+			Follows the same pattern as reading
+			100b would represent 32-bit mode
+
+		Only one bit is allowed to be set
+			Triggers <TODO> exception otherwise
+
+		No need for a jump instruction immediately after it
+
+PR (Privilege Register)
+	Consists of flags for specific privileges
+		Bit 0: Can configure everything
+		All other bits are to be configured at runtime
+
+	CPU initializes with it set to all 1s
+	Always readable
+	Writing directly is only allowed to remove permissions
+		Triggers <TODO> exception otherwise
+
+	Additional privileges can be granted by interrupts, exceptions and IRQs as configured by the IDT, EDT and IRQT, respectively
+
+FR (Feature Register)
+	Consists of various bit flags for different features that are currently enabled
+
+	See features/all.txt for a full list
+
+	Read only
+
+OFR (Optional Feature Register)
+	Consists of various bit flags for different features that can be enabled/disabled at runtime
+
+	See features/all.txt for a full list
+
+	On read:
+		Lists features that can be enabled/disabled
+
+	On write:
+		Sets the configurable features, and ignores bits for non-configurable ones
diff --git a/cpu/registers/general.txt b/cpu/registers/general.txt
new file mode 100644
index 0000000..1580fbf
--- /dev/null
+++ b/cpu/registers/general.txt
@@ -0,0 +1,13 @@
+There are <n> integer registers, named R0-<n-1>
+	All use two's compliment
+
+	There is an additional register, RS (Register Selector), that offsets the register number from its base
+		This register only has <bits required to store n-1> bits, and its overflow is never recorded
+
+	There is an additional register, RW (Register Window), that controls the number of integer registers available and preserved
+
+There are <n> float registers, named F0-<n-1>
+	There is an additional register, FS (Float Selector), that offsets the register number from its base
+		This register only has <bits required to store n-1> bits, and its overflow is never recorded
+
+	There is an additional register, FW (Float Window), that controls the number of float registers available and preserved
diff --git a/cpu/registers/hardware-interrupt-related.txt b/cpu/registers/hardware-interrupt-related.txt
new file mode 100644
index 0000000..895ff92
--- /dev/null
+++ b/cpu/registers/hardware-interrupt-related.txt
@@ -0,0 +1,5 @@
+OIP (Old Instruction Pointer)
+	Used to store the old IP when interrupts occur
+
+OPR (Old Privilege Register)
+	Used to store the old PR when interrupts occur
diff --git a/cpu/registers/pointers.txt b/cpu/registers/pointers.txt
new file mode 100644
index 0000000..e02db04
--- /dev/null
+++ b/cpu/registers/pointers.txt
@@ -0,0 +1,11 @@
+IP (Instruction Pointer)
+	Pointer to the current instruction being executed
+	It is not directly affected by OR
+
+	Read-only, can be set by certain jump instructions
+
+SP (Stack Pointer)
+	Pointer to the bottom of the stack (grows down) (used implicitly by push/pop instructions)
+
+BP (Base Pointer)
+	Pointer to the top of the stack (grows down) (used implicitly by push/pop instructions)
diff --git a/cpu/vulnerabilities/meltdown.txt b/cpu/vulnerabilities/meltdown.txt
new file mode 100644
index 0000000..fe354a7
--- /dev/null
+++ b/cpu/vulnerabilities/meltdown.txt
@@ -0,0 +1 @@
+13:06:53          * | \Test_User gets to reading about spectre/meltdown and adds a "GDTs/LDTs are stored directly on the CPU when loaded, and any speculation must check access first, and only to fetch/execute if it is allowed"
diff --git a/cpu/vulnerabilities/spectre.txt b/cpu/vulnerabilities/spectre.txt
new file mode 100644
index 0000000..fe354a7
--- /dev/null
+++ b/cpu/vulnerabilities/spectre.txt
@@ -0,0 +1 @@
+13:06:53          * | \Test_User gets to reading about spectre/meltdown and adds a "GDTs/LDTs are stored directly on the CPU when loaded, and any speculation must check access first, and only to fetch/execute if it is allowed"