Added incomplete instruction set overview, fixed some other stuff

7 files changed, 48 insertions, 6 deletions

diff --git a/cpu/access_control/gdt.txt b/cpu/access_control/gdt.txt
index fcadb5d..b129e05 100644
--- a/cpu/access_control/gdt.txt
+++ b/cpu/access_control/gdt.txt
@@ -1,5 +1,5 @@
 Each entry is n*4 bits long, where n is the current mode in bits
-TODO: Specifiy a limit for them
+TODO: Specify a limit for them
 
 It uses the following format:
 	(higher address)
diff --git a/cpu/instructions/overview.txt b/cpu/instructions/overview.txt
new file mode 100644
index 0000000..95b0034
--- /dev/null
+++ b/cpu/instructions/overview.txt
@@ -0,0 +1,41 @@
+Dynamic VLIW
+	Allows a dynamic number of instructions to be queued for simultaneous execution
+
+	All inputs within the same queue will be calculated before outputs
+		`mov R0, R1` and `mov R1, R0` put into the same queue will result in swapping R0 and R1
+
+	If any exception occurs during the execution of the queued instructions, all output will be discarded
+	If multiple exceptions would have theoretically occurred, which one is triggered is undefined
+
+	Current format ideas:
+		A)
+			effects:
+				uses space efficiently when using many repetitions of the same opcodes
+				easier for the CPU to parse
+
+				requires all parameter lengths to be the same within the opcode
+				wastes space when few repetitions of the same opcode exists
+
+			format:
+				num_opcodes
+				for each:
+					opcode
+					num_instructions
+					for each:
+						parameters
+				size_of_immediate_references
+				for each:
+					value
+
+		B) 
+			effects:
+				allows variable length parameters
+
+				harder for the CPU to parse
+
+			format:
+				size_of_queue
+				for each instruction:
+					opcode
+					parameters
+					immediate references
diff --git a/cpu/interrupts/exceptions/execution.txt b/cpu/interrupts/exceptions/execution.txt
index c20dd5f..dbf8825 100644
--- a/cpu/interrupts/exceptions/execution.txt
+++ b/cpu/interrupts/exceptions/execution.txt
@@ -4,6 +4,7 @@ For non-double exceptions:
 	PR is set to all 1s
 
 	Hardware interrupts will not occur until after the current processing has been finished via `irete`
+	Any exceptions that occur before `irete` will trigger a double exception instead of the normal one
 
 	When returning via irete:
 		PR is set to OPRE
@@ -18,7 +19,7 @@ For a double exception:
 
 	If any exceptions occur during execution of the double exception handler:
 		If this is not the only core active on the system:
-			Broadcasts a tripple fault message
+			Broadcasts a triple fault message
 			Shuts down
 
 		If this is the only core active on the system:
diff --git a/cpu/interrupts/hardware/execution.txt b/cpu/interrupts/hardware/execution.txt
index 2ee7c79..1644994 100644
--- a/cpu/interrupts/hardware/execution.txt
+++ b/cpu/interrupts/hardware/execution.txt
@@ -1,4 +1,4 @@
-When a hardware interrut occurs:
+When a hardware interrupt occurs:
 	OPRH gets set to the PR from the previous code running
 	OIPH gets set to the IP from the previous code running
 	PR is set to all 1s
diff --git a/cpu/interrupts/software/idt.txt b/cpu/interrupts/software/idt.txt
index 04cafd9..7488808 100644
--- a/cpu/interrupts/software/idt.txt
+++ b/cpu/interrupts/software/idt.txt
@@ -1,4 +1,4 @@
-Each enty is n*2 bits long, where n is the current mode in bits
+Each entry is n*2 bits long, where n is the current mode in bits
 TODO: Specify a limit for them
 
 It uses the following format:
diff --git a/cpu/registers/config.txt b/cpu/registers/config.txt
index 2be32a1..d32a47e 100644
--- a/cpu/registers/config.txt
+++ b/cpu/registers/config.txt
@@ -5,7 +5,7 @@ MR (Mode Register)
 
 	On read
 		Gives supported modes
-			If ((1 << ([desired mode in bytes] - 1)) & cr0) != 0, then it is supported
+			If ((1 << ([desired mode in bytes] - 1)) & MR) != 0, then it is supported
 
 			Support for 16-bit mode, 64-bit mode, 128-bit mode, and 256 bit mode would be represented as 111010b
 
diff --git a/cpu/registers/interrupt-related.txt b/cpu/registers/interrupt-related.txt
index dd4b0b8..62376e3 100644
--- a/cpu/registers/interrupt-related.txt
+++ b/cpu/registers/interrupt-related.txt
@@ -10,7 +10,7 @@ OIPE (Old Instruction Pointer [Exception])
 OPRE (Old Privilege Register [Exception])
 	Used to store the old PR when (non-double) exceptions occur
 
-OIPDE (Old Instriction Pointer [Double Exception])
+OIPDE (Old Instruction Pointer [Double Exception])
 	Used to store the old IP when double exceptions occur
 
 OPRDE (Old Privilege Register [Double Exception])