added basics for exceptions (incomplete)

5 files changed, 54 insertions, 9 deletions

diff --git a/cpu/interrupts/exceptions/edt.txt b/cpu/interrupts/exceptions/edt.txt
new file mode 100644
index 0000000..f1f5792
--- /dev/null
+++ b/cpu/interrupts/exceptions/edt.txt
@@ -0,0 +1,4 @@
+Each entry is n bits long, where n is the current mode in bits
+TODO: Specify a limit for them
+
+Each entry is a pointer to the code to be executed
diff --git a/cpu/interrupts/exceptions/execution.txt b/cpu/interrupts/exceptions/execution.txt
new file mode 100644
index 0000000..c20dd5f
--- /dev/null
+++ b/cpu/interrupts/exceptions/execution.txt
@@ -0,0 +1,29 @@
+For non-double exceptions:
+	OPRE gets set to the PR from the previous code running
+	OIPE gets set to the IP from the previous code running
+	PR is set to all 1s
+
+	Hardware interrupts will not occur until after the current processing has been finished via `irete`
+
+	When returning via irete:
+		PR is set to OPRE
+		Execution jumps to OIPE
+
+For a double exception:
+	OPRDE is set to the PR from the previous code running
+	OIPDE is set to the IP from the previous code running
+	PR is set to all 1s
+
+	Segmentation is ignored for the double exception handler, flat addressing is used with no protection
+
+	If any exceptions occur during execution of the double exception handler:
+		If this is not the only core active on the system:
+			Broadcasts a tripple fault message
+			Shuts down
+
+		If this is the only core active on the system:
+			Restarts the system
+
+	When returning via iretde:
+		PR is set to OPRDE
+		Execution jumps to OIPDE
diff --git a/cpu/interrupts/hardware/execution.txt b/cpu/interrupts/hardware/execution.txt
index c3cc5f5..2ee7c79 100644
--- a/cpu/interrupts/hardware/execution.txt
+++ b/cpu/interrupts/hardware/execution.txt
@@ -1,10 +1,10 @@
 When a hardware interrut occurs:
-	OPR gets set to the PR from the previous code running
-	OIP gets set to the IP from the previous code running
+	OPRH gets set to the PR from the previous code running
+	OIPH gets set to the IP from the previous code running
 	PR is set to all 1s
 
 The next hardware interrupt will not occur until after the current processing has been finished via `ireth`
 
 When returning via ireth:
-	PR is set to OPR
-	Execution jumps to OIP
+	PR is set to OPRH
+	Execution jumps to OIPH
diff --git a/cpu/registers/hardware-interrupt-related.txt b/cpu/registers/hardware-interrupt-related.txt
deleted file mode 100644
index 895ff92..0000000
--- a/cpu/registers/hardware-interrupt-related.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-OIP (Old Instruction Pointer)
-	Used to store the old IP when interrupts occur
-
-OPR (Old Privilege Register)
-	Used to store the old PR when interrupts occur
diff --git a/cpu/registers/interrupt-related.txt b/cpu/registers/interrupt-related.txt
new file mode 100644
index 0000000..dd4b0b8
--- /dev/null
+++ b/cpu/registers/interrupt-related.txt
@@ -0,0 +1,17 @@
+OIPH (Old Instruction Pointer [Hardware])
+	Used to store the old IP when hardware interrupts occur
+
+OPRH (Old Privilege Register [Hardware])
+	Used to store the old PR when hardware interrupts occur
+
+OIPE (Old Instruction Pointer [Exception])
+	Used to store the old IP when (non-double) exceptions occur
+
+OPRE (Old Privilege Register [Exception])
+	Used to store the old PR when (non-double) exceptions occur
+
+OIPDE (Old Instriction Pointer [Double Exception])
+	Used to store the old IP when double exceptions occur
+
+OPRDE (Old Privilege Register [Double Exception])
+	Used to store the old PR when double exceptions occur