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| author | Test_User <hax@andrewyu.org> | 2022-11-16 09:55:43 -0500 |
|---|---|---|
| committer | Test_User <hax@andrewyu.org> | 2022-11-16 09:55:43 -0500 |
| commit | b353a1f88da821e80183f613bc8179b1d0b2fdf9 (patch) | |
| tree | ccf94ea4042b6a3d715cdd86ff1b03d352c59108 | |
| parent | 724b2654fb10fa40cf9053d96012e860cf24623d (diff) | |
| download | specification-b353a1f88da821e80183f613bc8179b1d0b2fdf9.tar.gz specification-b353a1f88da821e80183f613bc8179b1d0b2fdf9.zip | |
Dynamic VLIW definition continued, fixed another missing thing
| -rw-r--r-- | cpu/access_control/gdt.txt | 2 | ||||
| -rw-r--r-- | cpu/instructions/overview.txt | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/cpu/access_control/gdt.txt b/cpu/access_control/gdt.txt index b129e05..a669dc4 100644 --- a/cpu/access_control/gdt.txt +++ b/cpu/access_control/gdt.txt @@ -68,3 +68,5 @@ permissions required: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 permissions not allowed: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 must not have 1st or 2nd permission to use this segment + +Access MUST be checked prior to any action, speculative or otherwise diff --git a/cpu/instructions/overview.txt b/cpu/instructions/overview.txt index 95b0034..9708e27 100644 --- a/cpu/instructions/overview.txt +++ b/cpu/instructions/overview.txt @@ -5,7 +5,11 @@ Dynamic VLIW `mov R0, R1` and `mov R1, R0` put into the same queue will result in swapping R0 and R1 If any exception occurs during the execution of the queued instructions, all output will be discarded + If multiple exceptions would have theoretically occurred, which one is triggered is undefined + If outputs from multiple instructions overlap, which one is written to the overlapping area is undefined + If an exception would be generated by attempting to write one value there but not the other, the exception might not occur if the other value is what is written in the end + This includes indirect writes via instructions such as `jmp` and `push` Current format ideas: A) @@ -39,3 +43,7 @@ Dynamic VLIW opcode parameters immediate references + + A minimum of <n> instructions must be accepted by all CPUs + TODO: define n + Specific implementations may accept more, up to the maximum specifiable by the format |