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| author | Test_User <hax@andrewyu.org> | 2023-01-21 02:37:18 -0500 |
|---|---|---|
| committer | Test_User <hax@andrewyu.org> | 2023-01-21 02:37:18 -0500 |
| commit | e46a052aade6e343fb8482fff9183589bbbfad8d (patch) | |
| tree | f817a32d60d1e29a5574f08fe1e05aa6fd01aa57 | |
| parent | 0d290b91117fb0002e247b7a48a38eb40fc48fbd (diff) | |
| download | specification-e46a052aade6e343fb8482fff9183589bbbfad8d.tar.gz specification-e46a052aade6e343fb8482fff9183589bbbfad8d.zip | |
All general-purpose registers can be used for integer arithmatic or floating-point arithmatic, no need to seperate them
| -rw-r--r-- | cpu/registers/general.txt | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/cpu/registers/general.txt b/cpu/registers/general.txt index 1580fbf..4859e9d 100644 --- a/cpu/registers/general.txt +++ b/cpu/registers/general.txt @@ -1,13 +1,8 @@ -There are <n> integer registers, named R0-<n-1> - All use two's compliment +There are <n> general purpose registers, named R0-<n-1> - There is an additional register, RS (Register Selector), that offsets the register number from its base - This register only has <bits required to store n-1> bits, and its overflow is never recorded +RS (Register Selector) + Offsets the register number from its base + This register only has <bits required to store n-1> bits - There is an additional register, RW (Register Window), that controls the number of integer registers available and preserved - -There are <n> float registers, named F0-<n-1> - There is an additional register, FS (Float Selector), that offsets the register number from its base - This register only has <bits required to store n-1> bits, and its overflow is never recorded - - There is an additional register, FW (Float Window), that controls the number of float registers available and preserved +RW (Register Window) + controls the number of general purpose registers available and preserved |